From 81f6ece30244166745821ce1f392b890493e1d38 Mon Sep 17 00:00:00 2001
From: Rodrigo Arias Mallo <rodarima@gmail.com>
Date: Thu, 21 Nov 2024 18:49:29 +0100
Subject: Add picture of Dillo on a FPGA RISC-V CPU

---
 gallery/index.html | 11 +++++++++++
 1 file changed, 11 insertions(+)

(limited to 'gallery/index.html')

diff --git a/gallery/index.html b/gallery/index.html
index d6f1cba..80854cb 100644
--- a/gallery/index.html
+++ b/gallery/index.html
@@ -215,6 +215,17 @@ email to <a href="mailto:dillo-dev@mailman3.com">dillo-dev@mailman3.com</a>.
 <h2>Screenshots</h2>
 <p>Screenshots of Dillo taken from the device itself.</p>
 
+<figure>
+  <a href="img/fpga-rv32.jpg">
+    <img alt="Dillo running on a FPGA" src="thumb/fpga-rv32.jpg"></a>
+  <figcaption>
+    <b>2024-11-20</b> -
+    Dillo 3.1.1 on a FPGA RISC-V CPU at 100 MHz with 64 MiB of RAM.
+    [<a href="http://www.fleasystems.com/">1</a>,
+	<a href="https://github.com/SpinalHDL/VexRiscv">2</a>].
+  </figcaption>
+</figure>
+
 <figure>
   <a href="img/macos-tiger.png">
     <img alt="Dillo running on Mac OS X Tiger 10.4" src="thumb/macos-tiger.jpg">
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